1. Field of the Invention
The present invention relates to processors. More specifically, this invention relates to controlling the instruction execution speed of a processor to ensure backward compatibility with existing software.
2. Background Information
As processors gain more capability, such as the ability to execute at higher speeds, and/or the ability to accept more bits of information than prior processors, compatibility with existing software is called into question. For instance, certain software may require that the system operate at a certain rate so that results and/or other information may be available in a predetermined period of time. For instance, some computer games require that a processor operate at a certain rate.
Although the current trend is to increase the performance, and thus, the throughput of most computer systems, there are some situations in which a user may desire to run the system at a lower instruction execution rate to ensure software compatibility. Prior art systems typically use adjustable clock rates on microprocessors to vary the speed between one rate and another. Therefore, in one example, if a processor is currently running at 33 MHz, the user may slow down the processor to a clock speed of 20 MHz. However, such systems typically require multiple clock crystals and/or other circuitry to allow this to occur. In addition, the range of clock speeds available in such systems typically is limited to two or three speeds in the system. If the user wishes to slow the processor and thus overall execution speed of the computer system even further, he may be required to install a different clock crystal. Thus, the predominant prior an method for slowing the execution speed of a processor and thus a computer system is to make extensive hardware modifications to a system. Alternatively, systems having multiple clock operating frequencies typically are limited to one or two clock speeds, and require additional circuitry to facilitate the operation at the various clock frequencies. Thus, the prior art provides no means for operating at a variety of instruction execution rates for providing the maximum software compatibility for the full range of software products and the full range of computer systems using a variety of microprocessors.